1. Field of the Invention
The present invention relates to a technique for carrying out high-speed transmission of signals between LSIs or between devices formed by a plurality of LSIs. More particularly, the present invention relates to a multiplexer circuit that converts parallel data into serial data.
2. Description of the Related Art
Recently, the performance of components used in computers and other information processing apparatuses has been greatly improved. In particular, dramatic improvements have been made, for example, in the performance of processors and semiconductor memory devices such as SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories). The improvements in the performance of semiconductor memory devices, processors, and the like have come to the point where system performance cannot be improved further unless the speed of signal transmission between components or elements is increased.
Further, in recent years, along with the increase in the operation speed of LSIs, it has become necessary to provide a signal transmission system that can perform high-speed transmission of large-capacity signals between LSIs or between devices constructed of a plurality of LSIs. For example, in network infrastructures, high-speed transmission in the order of gigabits per second (Gbps) is required. As a result, a focus has been placed on a device called a “giga-bit SerDes (serializer and deserializer)”.
In the interface circuit that has the SerDes function, it is necessary to convert relatively low-speed parallel data received from a logic circuit that carries out a data processing like a network switching, into high-speed serial data at Gbps speed, and output the converted data, for example. As the data speed has become so fast, it has become necessary to improve time constants by preparing a separate current path, at a portion that has an upper limit in the operation frequency within the LSI circuit. Alternatively, it has become necessary to reduce a power source inductance portion, by using differential signals, in the data processing inside the LSI.
Conventionally, a multiplexer circuit that converts parallel data into serial data carries out data processing by using multi-phase clock signals, as described in “DIGITAL SYSTEMS ENGINEERING”, Cambridge, 1998, by W, Dally et al. (for example, FIGS. 11–22 and FIGS. 11–25). In the conventional multiplexer circuits, it has been difficult to realize high-speed operation.
The prior art and its associated problems will be described in detail later with reference to relevant drawings.